A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE[0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. An interconnect bus transaction is synchronized in background so that a current cycle is not delayed. A first write cycle 1500 is completed as a no-wait state transaction, while immediately following second write cycle 1510 is delayed while synchronization circuit 1400 completes the synchronization of the first write cycle. nSTROBE pulse 1520 indicates first write transaction 1500 while nREADY pulse 1530 indicates the completion of a no-wait state first write transaction 1500. nSTROBE 1521 indicates the beginning of the second write transaction 1510 while nREADY pulse 1531 indicates the completion of a wait stated write, transaction 1510. Synchronization of write transaction 1600 is completed in background by using nSTROBE pulses 1521 and 1522 without the need for a free running clock signal from the host.