Given a parallel bus of data bits, a clock bit, a bid/busy bit, and an ack bit, and given a plurality of port devices coupled to the bus, a clock signal is used to synchronize messages on the bus and to divide the time domain into timeslots. No frame reference is used, and traffic on the bus is controlled using a protocol. Each port has an address which is one of the data bits of the bus. Ports bid for access to the bus by asserting their data line and the bid/busy line whenever the bid/busy line is not asserted by another. After seizing the bus, a source port keeps the bid/busy line asserted until it is done transmitting. When two or more ports bid for bus access at the same time, access is given to the port with the highest priority. Priority may be associated with the bit number.