Memory controller and method control method, and rendering device and printing device using the same

   
   

A rendering processor has source, pattern, destination prefetch/write units and DMA controllers. Each DMA controller enqueues a transaction such as a memory read/write in a transaction queue. A memory controller processes transactions in the queue in the FIFO order. A prefetch unit determines whether or not data is prefetched to a line end, and if the determination is affirmative, postpones a prefetch until completion of the write-back of the prefetched data.

Представляя обработчик имеет источник, картину, блоки назначения prefetch/write и регуляторы dma. Каждый регулятор dma enqueues трудыы such as read/write памяти в косе трудыов. Регулятор памяти обрабатывает трудыы в косе в заказе fifo. Блок prefetch обусловливает ли или не данные prefetched к концу линии, и если определение утвердительно, то откладывает prefetch до тех пор пока завершение write-back prefetched данные.

 
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