A synchronous dynamic random access memory controller has a high speed
interface and a low speed interface. The high speed interface has a buffer
with entries for receiving transactions, and the buffer has a valid bit
for each entry. The entries store transactions that are received from a
high speed bus. The low speed interface retrieves transactions from the
buffer. The high speed interface and low speed interface each have state
machines that synchronize the high speed and low speed interfaces using
the valid bit for each of the entries.
