To maximize the effective use of on-chip cache, a method and system for
exclusive two-level caching in a chip-multiprocessor are provided. The
exclusive two-level caching in accordance with the present invention
involves method relaxing the inclusion requirement in a two-level cache
system in order to form an exclusive cache hierarchy. Additionally, the
exclusive two-level caching involves providing a first-level tag-state
structure in a first-level cache of the two-level cache system. The first
tag-state structure has state information. The exclusive two-level caching
also involves maintaining in a second-level cache of the two-level cache
system a duplicate of the first-level tag-state structure and extending
the state information in the duplicate of the first tag-state structure,
but not in the first-level tag-state structure itself, to include an owner
indication. The exclusive two-level caching further involves providing in
the second-level cache a second tag-state structure so that a simultaneous
lookup at the duplicate of the first tag-state structure and the second
tag-state structure is possible. Moreover, the exclusive two-level caching
involves associating a single owner with a cache line at any given time of
its lifetime in the chip-multiprocessor.
