An integrated circuit constructed for easy debug and emulation includes a
function clock circuit and an operation circuit operating in synchronism
with a function clock. A trace trigger circuit triggers trace operation
upon detection of a predetermined condition within the operation circuit.
A FIFO buffer receives the trace data which is exported via a trace port.
The integrated circuit includes an oscillator clock circuit which may be
synchronized with the function clock or a reference clock. The oscillator
clock circuit operates in several modes selected by an externally
writeable control register. The clock circuit synchronizes with the
function clock signal or a reference clock signal as selected by the
control register. Pre-scalers are employed in two paths to scale the
oscillator clock frequency. The clock circuit also includes calibration
and test modes selected by the control register.
