The present invention generally relates to a processing system and method
for coalescing instruction data to efficiently detect data hazards between
instructions of a computer program. In architecture, the system of the
present invention utilizes a plurality of pipelines, coalescing circuitry,
and hazard detection circuitry. The plurality of pipelines is configured
to process instructions of a computer program, and the coalescing
circuitry is configured to receive, from the pipelines, a plurality of
register identifiers identifying a plurality of registers. The coalescing
circuitry is configured to coalesce said register identifiers thereby
generating a coalesced register identifier identifying each of said
plurality of registers. The hazard detection circuitry is configured to
receive the coalesced register identifier and to perform a comparison of
the coalesced register identifier with other information received from the
pipelines. The hazard detection circuitry is further configured to detect
a data hazard based on the comparison.
