A synchronous semiconductor memory device has a memory section which
includes a memory cell array having a plurality of memory cells and which
is capable of a read operation of reading information from the memory
cells according to a read command and a write operation of writing
information into the memory cells according to a write command. The
synchronous semiconductor memory device further has a command sensing
circuit which senses whether a first command inputted in synchronization
with an external clock signal is the read command or the write command.
The synchronous semiconductor memory device further has a bank timer
circuit which, when the command sensing circuit has sensed either the read
command or the write command, sets the end time of the restore operation
of a row address strobe (RAS) and the start time of the precharge
operation of the RAS according to the external clock signal.
