A digital system and method of operation is provided in which the digital
system has at least one processor, with an associated multi-segment cache
memory circuit (506(n). Validity circuitry (VI) is connected to the memory
circuit and is operable to indicate if each segment of the plurality of
segments holds valid data. Dirty bit circuitry (DI) is connected to the
memory circuit for indicating if data within the cache is incoherent with
a secondary back-up memory. DMA circuitry can transfer (1652) blocks of
data/instructions (1660) between the cache and a secondary memory (1602).
A transfer mode circuit (1681) controls how DMA operations are affected by
the dirty bits. If the transfer mode circuit is in a first mode, a DMA
operation transfers only segments (1661) indicated as dirty (1685). If the
transfer mode circuit is in a second mode, a DMA operation transfers and
entire block of data (1660) without regard to dirty indicators (1686). DMA
transfers from the cache to secondary memory are thereby configured to be
responsive to the dirty bits. A dirty bit mode circuit (1680) controls how
DMA transfers affect the dirty bits. When the mode circuit is in a first
mode, DMA transfers set the affected dirty bits to a clean state. When the
dirty bit mode circuitry is in an alternate mode, DMA transfers set the
affected dirty bits to a dirty state. A cache clean operation will thus
copy data provided by a DMA transfer and indicated as dirty into backup
secondary memory.
