A voltage-mode pulse width modulation (PWM) VLSI implementation of neural
networks, comprising: a voltage-pulse converter for converting an input
voltage into a neuron-state pulse; a synapse multiplier, including a
multiplier cell for multiplying the neuron-state pulse by an input weight
voltage and an integral and summation cell for integrating and summing up
the multiplied output and producing a first output voltage; and a sigmoid
circuit for converting the first output voltage into a second output
voltage with the non-linear activation function of neuron.
