A built-in self-test (BIST) system and method for testing an array of
embedded electronic devices, the BIST comprising: a shift register device
connected to an output pin of an embedded array of electronic devices
being tested and for receiving a failure indication signal at a real-time
output pin of the device under test, the shift register generating a
unique signature in response to receipt of the failure indication; a
device for determining whether the generated unique signature is
represented in a table comprising known signature values and corresponding
bitmaps of prior determined array defects for that device under test;
wherein the need to bitmap the array is avoided when a known failure
signature is determined.
