System for determining status of multiple interlocking FIFO buffer structures based on the position of at least one pointer of each of the multiple buffers

One embodiment of the present invention relates to a method for using at least two first-in, first-out ("FIFO") buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.