An address selection circuit in a synchronous memory device receives a
clock signal and an address signal, passes the received address signal
asynchronously from an address input circuit to an address decoder to
generate an address selection signal, then uses the same received address
signal to generate further address selection signals in synchronization
with the clock signal. This scheme enables the address selection signals
to be generated more quickly than if all address signal paths were
synchronized with the clock signal. In a burst access, even the first
address selection signal can be generated relatively quickly.
