A microprocessor architecture (310) has a plurality of functional units
arranged in a parallel manner between one or more source buses (412 and/or
414) and one or more result buses (490). At least one of the functional
units within the architecture is a content addressable memory (CAM)
functional unit (430) which can be issued CPU instructions via a sequencer
(480) much like any other functional unit. The operation of the CAM (430)
may be pipelined in one or more stages so that the CAM's throughput may be
increased to accommodate the higher clock rates that are likely used
within the architecture (310). One embodiment involves pipelining the CAM
operation in three stages (510, 520, and 530) in order to sequentially
perform data input and precharge operations, followed by match operations,
and followed Finally by priority encoding and data output.
