A parallel A/D converter includes: a reference-voltage generation circuit
for outputting m reference voltages ("m" is an integer of not less than
two), each having different voltage values, in response to the bit
precision of digital output signals; n comparators ("n" is an integer
smaller than "m"); and an encoder for encoding outputs of the n
comparators to output the digital output signals. Each of the n
comparators compares the magnitude of one of the m reference voltages with
that of an analog input signal. Thereby, power consumption can be reduced.
