A memory having a circuit including a built-in address counter with a test
mode. The address counter may be used to generate the memory array
addressing for the different array test patterns. The circuit may comprise
a logic circuit and a counter circuit. The logic circuit may be configured
to generate one or more control signals in response to one or more control
inputs. The counter circuit may be configured to generate a first counter
output and a second counter output in response to (i) the control outputs
and (ii) one or more inputs. The counter may comprise a first portion
configured to generate the first counter output and a second portion
configured to generate the second counter output.
