A tool for designing an integrated circuit and semiconductor product that
generates correct RTL for I/O buffer structures in consideration of the
requirements of diffused configurable I/O blocks and/or I/O hardmacs of
the product. Given either a slice description of a partially manufactured
semiconductor product, a designer can generate the I/O resources of an
application set. Then given an application set having a transistor fabric,
and the diffused configurable I/O blocks and/or the I/O hardmacs, and a
plurality of accompanying shells, the I/O generation tool herein
automatically reads a database having the slice description and generates
the I/O buffer structures from the transistor fabric. The I/O generation
tool further conditions and integrates input from either or both customer
having her/his own logic and requesting a specific semiconductor product
or from IP cores with their preestablished logic. The I/O generation tool
creates correct RTL from the transistor fabric for correct placement,
timing, testing, and function of I/O buffer amplifiers for the
semiconductor product, either incrementally or globally. Once I/O buffer
structures are created, they are qualified by a plurality of shells
including a verification shell, a static timing analysis shell, a
manufacturing test shell, and a RTL analysis shell.
