Dual stage communication processor

   
   

A communications processor is presented that is capable of receiving a potentially degraded data transmission signals operating at high transmission rates and generating an improved data transmission signal in a manner that allows the signals to be transmitted over longer distances than is otherwise possible using conventional methods. The communications processor includes a decoding mechanism configured to compensate for amplitude and phase distortions of the data transmission signal, to split the corrected data signal into component data signals, to generate a data clock reference signal based on the data transmission signal and the external clock reference signal, and to convert the component data signals into digital component data signals synchronized to the data clock reference signal. The communications processor further includes an encoding mechanism configured to receive the digital component data signals and the data clock reference signal and to convert the digital component data signals into analog component data signals. The communications processor then selectively outputs at least one of the analog component data signals as the improved data transmission signal.

 
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