A processor (300) in a distributed shared memory system (10) has ownership
of a cache line. The processor modifies the cache line and wishes to
update the home memory (17) of the cache line with the modification. The
processor (300) generates a return request for routing by a processor
interface (24). Meanwhile, a second processor (400) wishes to obtain
ownership of the cache line and sends a read request to a memory directory
(22) associated with the home memory (17) of the cache line. The memory
directory (22) generates an intervention request towards the processor
interface (24) corresponding to the last known location of the cache line.
The processor interface (24) has now forwarded the return request to the
memory directory (22) but subsequent to the read request from the second
processor (400). Rather than waiting for an acknowledgment from the memory
directory (22) that the return request has been processed, the processor
interface (24) sends an intervention response to the second processor that
includes the modified cache line.
