An integrated circuit substrate having embedded wire conductors provides
high-density interconnect structure for integrated circuits. Wires are
shaped to form a conductive pattern and placed atop a dielectric substrate
layer. Additional dielectric is electro-deposited over the wires to form
an insulating layer that encapsulates the wires. One or more power planes
may be embedded within the substrate and wires within the conductive
pattern may be laser-welded to vertical wire stubs previously attached to
a power plane. Vias may be formed by mechanically or laser drilling (or
plasma or chemical etching) through any power planes and screening a
copper paste into the drilled holes to form conductive paths through the
holes. Via conductors may then be exposed by a plasma operation that
removes dielectric, leaving the ends of the via conductors exposed. Wires
within the conductive pattern may then be laser-welded to the via
conductor ends.
