Disclosed is a digital VFO device which comprises a plurality of VFO
circuits 12 and 14; synchronous counters 12a and 14a installed in each VFO
circuits 12 and 14; and an adjusting circuit 110 selecting one of the VFO
circuits 12 and 14 based on signals 113 and 114 representing the peak
shift state of an input data 11 output from each VFO circuits. Correcting
instruction signals 16 and 17 are generated to correct the synchronous
counter of the other VFO circuits by substituting the counter value of the
synchronous counter of the VFO circuit selected by the adjusting circuit
110 for the synchronous counter of the other VFO circuits.
