A clocking circuit decreases the load on the local clock signals to save
power. The load is decreased by altering the structure of the latches.
Typically, a passgate style latch is used where both an NFET and a PFET
are used to control dataflow. Here, the PFET has been removed and the
load is decreased. However, it is difficult to pass a logical 1 through
an NFET and this increases both the rising slew and rising edge delay
through the latch. The effect is mitigated, though, by overdriving the
local clock block (LCB) local clocks to drive a local clock to the
latches by distribution passgates uning only NFET transistors in the
master latches and slave latches. Overdrivig the NFET gate allows the
NFET to pass a full-level logical 1 signal.
