One embodiment of the invention provides a system and a method for reducing
line end shortening during an optical lithography process for
manufacturing an integrated circuit. The system operates by receiving a
specification of the integrated circuit, wherein the specification defines
transistors that include gates. Next, the system identifies a gate within
the specification, wherein the gate includes an endcap that is susceptible
to line end shortening during the optical lithography process. The system
then extends a phase shifter used to form the gate, so that the phase
shifter defines at least a portion of the endcap and thereby reduces line
end shortening of the endcap due to optical effects.
