A superscalar processor having a content addressable memory structure that
transmits a first and second output signal is presented. The superscalar
processor performs out of order processing on an instruction set. From the
first output signal, the dependencies between currently fetched
instructions of the instruction set and previous in-flight instructions
can be determined and used to generate a dependency matrix for all
in-flight instructions. From the second output signal, the physical
register addresses of the data required to execute an instruction, once
the dependencies have been removed, may be determined.
