High density storage scheme for semiconductor memory

   
   

A memory device comprising a compression and decompression engine and a error detection and correction engine connected between a cache memory and a main memory in the same semiconductor chip.

Un dispositivo de memoria que abarcaba un motor de la compresión y de la descompresión y un motor de la detección y de la corrección de error conectó entre una memoria de escondrijo y una memoria central en la misma viruta del semiconductor.

 
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< Apparatus having durable storage

< Information processor, information processing method and information processing program and recording medium

> Memory controller with programmable configuration

> Cache having a prioritized replacement technique and method therefor

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