A method for informing a processor of a selected order of transmission of
data to the processor. The method comprises the steps of coupling system
components via a data bus to the processor to effectuate data transfer,
determining at the system component logic the order in which to transmit
data to the processor, and issuing to the data bus a selected order bit
concurrent with the data, wherein the selected order bit alerts the
processor of the order and the data is transmitted in that order. In a
preferred embodiment, the system component is the cache and the method may
involve receiving at the cache a preference of ordering for a read
address/request from the processor. The preference order logic of the
cache controller or a preference order logic component evaluates the
preference of ordering desired by comparing the processor preference with
other preferences, including cache order preference. One preference order
is selected and the data is then retrieved from a cache line of the cache
in the order selected.
