A testbench for an integrated circuit (IC) design including a chain of scan circuits
having a memory characteristic is verified by: (a) dividing the chain of scan circuits
and creating a plurality of partitions, each partition including at least one logic
cone output, each scan circuit belonging to one of the partition as a logic cone
output; (b) generating a partitioned netlist for each partition from a full netlist
for the IC design, the partitioned netlist including at least one logic cone, the
logic cone extending from the logic cone output to at least one logic cone input;
(c) generating a partitioned testbench for each partition from the full testbench
based on the partitioned netlists; and (d) performing verification for the testbench
by simulating the partitioned testbenches on the corresponding partitioned netlists.
