A symmetrical divide-by-2 circuit has a master latch made up of two inverters.
The circuit has an inverter on each output. The capacitance of these inverters
forms a dynamic slave latch that is connected to the master latch through a transmission
gate on each master latch output. The data is transferred from the master latch
to the dynamic slave latch every clock cycle by an enable clock and an inverse
of the enable clock. Capacitance leakage is reduced by the transmission gates until
the next clock cycle. The circuit is clocked by a one-shot clock that is self-aligning
to the latest transition of either the enable clock or inverse enable clock.
