In a semiconductor memory device including memory cells and a peripheral circuit
unit, a memory cell has a first gate structure formed on a semiconductor substrate;
a first impurity region of a first conductive type formed in the substrate on a
first side of the gate structure; and a second impurity region formed in the substrate
on a second side of the gate structure, the second impurity region including: a
third impurity region of the first conductive type, a fourth impurity region of
the first conductive type between the third impurity region and the second side
of the gate structure, and a halo ion region of a second conductive type formed
adjacent to the fourth impurity region.
