An apparatus comprising a first circuit, a second circuit, and a third circuit.
The first circuit may be configured to generate a plurality of control signals
and a select signal, in response to (i) a receive clock signal, (ii) a reference
clock signal and (iii) a master clock signal. The second circuit may be configured
to generate a read signal and a window signal in response to the plurality of control
signals. The third circuit may be configured to generate a lock signal in response
to (i) the reference clock signal, (ii) the select signal, (iii) the read signal
and (iv) the window signal. The receive clock signal and the reference clock signal
may be independent clocks configured to provide range control over one or more channels.
