The present invention is a monitor that detects a design verification event and
reports a status event to a database. One embodiment of the present invention comprises
a monitor declaration, zero or more signal declarations, zero or more bus declarations
and one or more logic expressions. A logic expression, formulated using the declared
signals and buses, is used to evaluate whether a specific verification event has
occurred. The present invention further comprises a monitor where the signal of
the signal declaration of the monitor is an N-Nary signal. Additionally, the present
invention comprises a parser to translate the monitor source file code into a standard
computer language code.
