Trace data is aligned in a processor having an instruction pipeline by delaying
write data and read data a predetermined number of clock cycles, selectively swapping
both most significant write data and read data with least significant write data
and read dependent upon memory access control data. The write and read data pass
normally for even memory bank accesses and are swapped for odd memory bank accesses.
Memory access control data, program counter data and program counter control data
are similarly delayed. At least the read data and optionally all the data are held
upon a pipeline stall.
