A system and method are provided that include determining optimum memory organization
in an electronic device, wherein further determined are optimum resource interconnection
patterns. One aspect of the system and method includes determining resource, e.g.,
memories and data paths, interconnection patterns of complex bus structures with
switches using system-level information about the data-transfer conflicts. The
quantity of memories within an electronic device, the size of the memories and
the interconnection between the memories, including the interconnection of the
memories with one or more data paths, defines a memory organization of an electronic
device. Another aspect of the system and method relates to selecting an optimized
memory organization, including selecting an optimized interconnection pattern between
the memories and between the memories and the data paths.
