Structures and methods involve dynamic enhancement mode p-channel flash
memories with ultrathin tunnel oxide thicknesses. Both write and erase operations
are performed by tunneling. The p-channel flash memory cell with thin tunnel oxides
will operate on a dynamic basis. The stored data can be refreshed every few seconds
as necessary. However, the write and erase operations will now be orders of magnitude
faster than traditional p-channel flash memory. Structures and methods for p-channel
floating gate transistors are provided that avoid p-channel threshold voltage shifts
and achieve source side tunneling erase. The p-channel memory cell structure includes
a floating gate separated from a channel region by an oxide layer of less than
50 Angstroms. The methods further include reading the p-channel memory cell by
applying a potential to a control gate of the p-channel memory cell of less than
1.0 Volt.
