An integrated circuit is provided comprising a latch circuit including, a first
inverter including a first high threshold voltage PMOS transistor and a first high
threshold voltage NMOS transistor with a first data node comprising interconnected
source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including
a second high threshold voltage PMOS transistor and a second high threshold voltage
NMOS transistor with a second data node comprising interconnected source/drains
(S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS
and first NMOS transistors are coupled to the second data node; wherein the gates
of the second PMOS and second NMOS transistors are coupled to the first data node;
a first low threshold voltage access transistor including a first S/D coupled to
the first data node and to the gate of the second PMOS transistor and to the gate
of the second NMOS transistor and including a second S/D coupled to a first data
access node and including a gate coupled to a first access control node; and a
second low threshold voltage access transistor including a first S/D coupled to
the second data node and to the gate of the first PMOS transistor and to the gate
of the first NMOS transistor and including a second S/D coupled to a second data
access node and including a gate coupled to a second access control node.
