A signal processing apparatus and method for up or down conversion of an interlace
signal with a high degree of accuracy. The frequency of a write system clock supplied
from a PLL circuit is divided by N by a dividing circuit and then multiplied by
M by a multiplying circuit to produce a readout system clock. An interpolation
circuit writes a video signal into a frame memory in synchronism with the write
system clock from the PLL circuit, and reads out the video signal in synchronism
with the readout system clock from the multiplying circuit.
