A timing generation circuit (15) is formed integrally on the same glass
substrate (11) together with a display area section (12) similarly
to an H driver (13U) and a V driver (14), and timing pulses to be
used by the H driver (13U) and the V driver (14) are produced based
on timing data produced by a shift register (31U) of the H driver (13U)
and a shift register (14A) of the V driver (14). The invention thereby
provides a timing generation circuit which can contribute to miniaturization and
reduction of the cost of the set and a display apparatus of the active matrix type
in which the timing generation circuit is incorporated.
