A higher TLB that stores TLB data required for translating a virtual address
into
a physical address. A higher address translator performs address translation based
on the TLB data according to an access. If address translation is not possible,
the higher address translator requests a lower address translator to carry out
the address translation. The lower address translator performs address translation
based on a lower TLB. A shift register outputs a write prohibit signal to prohibit
writing of the TLB data to the higher TLB, when write data that is the same as
the write data has already been written in the higher TLB.
