An apparatus comprising a memory, a plurality of modules, an address translation
unit and a controller. The memory may be arranged as a plurality of memory banks.
Each of the plurality of modules may be configured to generate one or more addresses
for accessing a particular one of the plurality of memory banks. The address translation
unit may be configured to modify the one or more addresses in response to a control
signal. The controller may be configured to generate the control signal in response
to a computer executable instruction.
