A memory system includes a memory device that includes an active termination
circuit.
The memory system further includes a controller circuit that includes a frequency
control circuit that is configured to modulate a system clock between a first frequency
value and a second frequency value, greater than the first frequency value, responsive
to a control signal. The controller circuit is further configured to determine
an active termination value for the active termination circuit responsive to the
system clock at the first frequency value, and to apply commands to the memory
device responsive to the system clock at the second frequency value.