Structures, systems and methods for memory cells utilizing trench bit
lines formed within a buried layer are provided. A memory cell is formed in a triple
well structure that includes a substrate, the buried layer, and an epitaxial layer.
The substrate, buried layer, and epitaxial layer include voltage contacts that
allow for the wells to be biased to a de voltage level. The memory cell includes
a transistor which is formed on the epitaxial layer, the transistor including a
source and drain region separated by a channel region. The trench bit line is formed
within the buried layer, and is coupled to the drain region of the transistor by
a bit contact.
