A method for testing a memory circuit selects each cell in a region of a cell
array
as a target cell and performs a test cycle which includes selecting the target
cell and neighboring cells which contain at least those cells for which is cannot
be ruled out that their operation causes a fault-producing interaction. A data
item is written to the target cell in order to produce one of two defined states.
A write signal is applied to the neighboring cells in order to produce an undefined
state which lies between the two defined states. The target cell and the neighboring
cells are then read and the result of the reading process is used to check whether
there is any interaction between the operation of the target cell and the operation
of the neighboring cells.
