A semiconductor memory device, in which peripheral circuits are arranged in a
cross
area of a semiconductor chip composed of the longitudinal center portions and the
transverse center portions, and in which memory arrays are arranged in the four
regions which are divided by the cross area. This structure in which the peripheral
circuits are arranged at the center portion of the chip permits the longest signal
transition paths to be shortened to about one half of the chip size to speed up
the DRAM which is intended to have a large storage capacity.
