A software/hardware hybrid video decoder, particularly suited for decoding MPEG
video, that takes advantage of processing capabilities of graphics coprocessors
to perform the motion compensation portion of video decoding. Motion compensation
is performed by bit block transfer (bit BLT) operations on the graphics coprocessor.
The bit BLT operations perform the addition of pixels in the reference and error
blocks. Bit BLT operations may also be used for interpolation between reference
blocks to provide subpixel resolution for motion vectors.
