An erase methodology of flash memory cells in a multi-bit memory array with bits
disposed in normal and complimentary locations. An erase verify of bits in the
normal locations is performed and if a bit in the normal location fails and if
the maximum erase pulse count has not been reached, erase pulses are applied to
both the normal bit and the complimentary bit. An erase verify of bits in the complimentary
locations is performed and if a bit in the complimentary location fails and if
the maximum erase pulse count has not been reached, erase pulses are applied to
both the complimentary and the normal bit locations. If the bits pass the erase
verify, the bits are subjected to a soft programming verify. If the bits are overerased
and if the soft programming pulse count has not been reached a soft programming
pulse is applied to the overerased bit.
