A cache memory includes a plurality of memory chips, or other separately addressable
memory sections, which are configured to collectively store a plurality of cache
lines. Each cache line includes data and an associated cache tag. The cache tag
may include an address tag which identifies the line as well as state information
indicating the coherency state for the line. Each cache line is stored across the
memory chips in a row formed by corresponding entries (i.e., entries accessed using
the same index address). The plurality of cache lines is grouped into separate
subsets based on index addresses, thereby forming several separate classes of cache
lines. The cache tags associated with cache lines of different classes are stored
in different memory chips. During operation, the cache controller may receive multiple
snoop requests corresponding to, for example, transactions initiated by various
processors. The cache controller is configured to concurrently access the cache
tags of multiple lines in response to the snoop requests if the lines correspond
to differing classes.
