An method of creating a physical layout of an integrated circuit. A schematic
file (600) is mapped directly to a physical layout using the location of
elements and routing of interconnections as specified in the schematic file (600).
The method takes advantage of constraints on the schematic design to provide the
layout file (675) quickly, without complex routing programs. Design rules
violations are anticipated and corrected in some cases. In other cases, the design
rule violations are annotated, if the designer intentionally placed them in the design.
