Various embodiments provide a decoder for a memory array, comprising an array
of address and output lines, vertical pillars, vertical floating gate transistors,
and buried source lines. Each pillar includes single crystalline first and second
contact layers separated by an oxide layer. Each floating gate transistor is formed
in a single crystalline layer, having a thickness less than 10 nanometers, selectively
disposed on a side of one of the pillars. Each transistor includes first and second
source/drain regions in contact with the first and second contact layers, respectively,
a body region opposing the oxide layer and contacting the first and second source/drain
regions, and a floating gate opposing the body region. The source lines are disposed
below the pillars and interconnect the first contact layer of pillars. Each of
the address lines is disposed between rows of pillars and serves as a control gate.
