A memory having gate structures adjacent opposing sidewalls of a semiconductor
structure including a channel region and a plurality of charge storage locations
between the gate structures and the opposing sidewalls. The channel region is located
between two current terminal regions, which in one example serve as the source/drain
regions. A memory cell can be implemented in an array of memory cells wherein one
gate structure is coupled to one word line and the other gate structure is coupled
to another word line. In one example, each cell includes four charge storage locations,
each for storing one bit of data.
