Systems and methods for placement of dummy metal fills while preventing disturbance
of device matching and optionally limiting capacitance increase are disclosed.
A computer-automated method for locating dummy fills in an integrated circuit fabrication
process generally comprises receiving an input layout of the integrated circuit
and specification of device matching for the integrated circuit and locating the
dummy fills in the integrated circuit according to dummy rules while preserving
device matching. Locating the dummy fills may include locating the dummy fills
along the at least one axis of symmetry where device matching is along an axis
of symmetry and locating the dummy fills so as to preserve matching of the repeated
elements where device matching is repeated matched elements. The method may also
include designating at least one net of the integrated circuit as a critical net,
the critical nets being only a subset of all nets of the integrated circuit, identifying
metal conductors corresponding to each designated critical net from the layout
file, and delineating a net blocking exclusion zone extending a distance of a minimum
net blocking distance (NBD) from the metal conductor for each metal conductor identified,
wherein the step of locating locates the dummy fills outside of the net blocking
exclusion zone.
